badge team, named designer group, and open-hardware source publisher
SemiTO-V identifies itself publicly as a Polytechnic of Turin RISC-V student team and publishes the event-associated RISC-V FPGA Badge sources. This credit does not claim organizer ownership, full distribution control, or image-reuse authority.
Source
named badge designer
Named in the project README's designer credit list. The source does not assign a narrower individual hardware, firmware, FPGA, artwork, manufacturing, or fulfilment role.
Source
named badge designer
Named in the project README's designer credit list. The source does not assign a narrower individual hardware, firmware, FPGA, artwork, manufacturing, or fulfilment role.
Source
named badge designer
Named in the project README's designer credit list. The source does not assign a narrower individual hardware, firmware, FPGA, artwork, manufacturing, or fulfilment role.
Source
named badge designer
Named in the project README's designer credit list. The source does not assign a narrower individual hardware, firmware, FPGA, artwork, manufacturing, or fulfilment role.
Source
named badge designer
Named in the project README's designer credit list. The source does not assign a narrower individual hardware, firmware, FPGA, artwork, manufacturing, or fulfilment role.
Source
named badge production and assembly partner
SemiTO-V's public Developer Zone material says NextPCB produced the boards. This is a narrow team-stated production-context credit, not a claim of recipient delivery, product support, or image-reuse authority.
Source
summit context publisher and named project sponsor
Official RISC-V summit pages establish the Bologna event, and the project README names RISC-V International as a sponsor. This credit does not assert ownership of the SemiTO-V repository, attendee-wide issuance, or image permission.
Source
Why It Mattered
It adds a concrete European open-hardware developer-event badge with named designers, OSHWA certification, native KiCad design sources, a CERN-OHL-W hardware-license trail, and a limited distribution account, while preserving the distinction between summit prototypes and a later current repository revision.
Hardware
SemiTO-V's public Developer Zone material identifies an RP2350 microcontroller and a GOWIN GW1N-9 FPGA. The repository contains a KiCad 10 PCB and native schematic set, but the reviewed material does not map its current post-event source revision to each physical summit unit or establish a complete production BOM, component population, power architecture, electrical limits, safety assessment, test result, enclosure, connector map, or final device configuration.
Software & Apps
The project README links public pico2-editor and riscv-badge-displaylib firmware references, while team posts state that the badge used custom firmware with a default RV32I core. The public repository has no tag or GitHub release and its current source has post-event revisions. This dossier records the source at a high level without providing programming, FPGA-loading, debugging, or operating instructions or claiming that a current checkout was deployed on event hardware.
Lore
RISC-V International's public summit material thanks participants for joining the completed Bologna event. SemiTO-V says it volunteered in the Developer Zone, planned a 25-board workshop allocation, and faced a logistics delay at the start of the summit. The public hardware archive later received an August Version 1.6 update addressing board issues and silkscreen changes. A team statement about an event prototype and a future complete revision therefore keeps the physical summit artifact distinct from the current source tree.
documented hardware core
primary team source detail
SemiTO-V identifies an RP2350 microcontroller and GOWIN GW1N-9 FPGA for the badge. The record does not infer unlisted peripherals, power behavior, safety limits, complete bill of materials, or exact population of every physical unit.
Compatibility: SemiTO-V RISC-V FPGA Badge
Source
firmware reference links
README-linked projects; deployed build unrecovered
The README points to pico2-editor and riscv-badge-displaylib. This record preserves their public-reference role without asserting version parity, a released binary, a deployed event image, programming steps, support ownership, or a recovery procedure.
Compatibility: riscv-fpga-badge-2026 README
Source
hardware source archive
public native source
The repository README identifies KiCad 10 and the archive exposes native PCB and schematic files. The open source tree is valuable documentation, but it is not a substitute for a reconciled physical production revision, assembly record, electrical-safety assessment, or delivery ledger.
Compatibility: riscv-fpga-badge-2026 repository
Source
high-level firmware capability
primary team source detail
The team says the custom firmware includes a default RV32I core. This is recorded as high-level source context only, without operational FPGA configuration, programming, debugging, execution, or security claims.
Compatibility: SemiTO-V RISC-V FPGA Badge
Source
limited event initiative
25 boards planned; completed recipient handoff unrecovered
SemiTO-V stated it would bring 25 badges to the Developer Zone workshop and later reported a logistics problem that prevented intended June 8 distribution. The sources establish a limited 25-unit Developer Zone badge run in planning and a real physical-board project, not a completed allocation ledger, attendee-wide issue, or confirmed recipient count.
Compatibility: RISC-V Summit Europe 2026 Developer Zone
Source
revision boundary
August 3, 2026 source update; event-unit parity unconfirmed
Version 1.6 fixes listed in the August source commit demonstrate that the public design continued after the June summit. The current post-event V1.6 KiCad revision is therefore not presented as a photograph, render, or authoritative specification of every physical summit badge.
Compatibility: riscv-fpga-badge-2026 Version 1.6
Source
final hardware, power, and electrical-safety gap
note
The catalogue preserves the source-backed design trail without calling it a fabrication recipe, tested device specification, safety assessment, or compatibility guarantee.
- Confidence
- public source archive review
- Status
- native source visible; production/safety evidence unrecovered
- Timeframe
- current catalogue build
- Source note
- SemiTO-V repository tree, KiCad sources, README, and primary team posts.
firmware release and deployed-build gap
note
The record describes public firmware context at a high level without presenting any current source checkout as deployed, supported, verified, or suitable for operation.
- Confidence
- README and repository-state review
- Status
- public references visible; event build unrecovered
- Timeframe
- source pass on 2026-08-04
- Source note
- RISC-V FPGA Badge README, repository metadata, and SemiTO-V Developer Zone post.
individual manufacturing and delivery-role boundary
note
The dossier credits named contributors and the stated production partner without inferring sole authorship, manufacture responsibility, fulfilment ownership, product-support duty, or image authority.
- Confidence
- named design and production-context sources
- Status
- team/design credits and named production partner recorded; role allocation incomplete
- Timeframe
- current catalogue build
- Source note
- RISC-V FPGA Badge README; SemiTO-V Developer Zone and production updates.
license, sponsorship, and event-endorsement boundary
note
The catalogue links the source-license and sponsorship context while keeping organizer ownership, attendee credential status, trademark/endorsement scope, physical-delivery responsibility, and image rights separate.
- Confidence
- README and team-source statements
- Status
- hardware-license and named-sponsor claims recorded narrowly
- Timeframe
- current catalogue build
- Source note
- RISC-V FPGA Badge README; SemiTO-V project updates; official RISC-V Summit pages.
limited Developer Zone allocation and fulfilment gap
note
The catalogue does not turn a limited planned workshop allocation into proof that all 25 boards, all workshop participants, or all summit attendees received a badge.
- Confidence
- primary team event updates
- Status
- 25 boards planned; logistics delay published; recipient outcome unrecovered
- Timeframe
- RISC-V Summit Europe 2026
- Source note
- SemiTO-V Developer Zone post and public team update feed.
missing rights-cleared image
note
The record remains source-backed and image-free rather than copying repository renders, team social media, event media, screenshots, logos, or approximate/generated imagery.
- Confidence
- local project policy and source-revision review
- Status
- needs a rights-cleared, event-unit-specific original or upstream render
- Timeframe
- current catalogue build
- Source note
- badge.gallery image policy; SemiTO-V repository README, assets/history, and Version 1.6 commit review.
summit prototype and post-event source-revision boundary
note
Current open design sources are linked for research but are not represented as the definitive exact event-unit design, final production revision, or a factual image of every distributed unit.
- Confidence
- primary team statement and dated repository history
- Status
- physical initiative established; exact current-source-to-unit mapping unrecovered
- Timeframe
- June-August 2026
- Source note
- SemiTO-V Developer Zone and prototype updates; riscv-fpga-badge-2026 Version 1.6 commit.