Hacker Con Badges

RISC-V Summit Europe

RISC-V Summit Europe 2026

The completed June 8-12, 2026 RISC-V Summit Europe in Bologna, with core summit sessions June 9-11 and Developer Workshops on June 8. SemiTO-V documented a limited Developer Zone RISC-V FPGA badge project prepared for the event, while delivery/receipt and exact final production-revision evidence remain incomplete.

Palazzo dei Congressi, Piazza della Costituzione 4/A, Bologna, Italy · Italy · 2026

RISC-V Summit Europe 2026 FPGA Badge

SemiTO-V's RISC-V FPGA Badge was a limited Developer Zone electronic PCB badge project for RISC-V Summit Europe 2026 in Bologna. Primary team sources name an RP2350 MCU, a GOWIN GW1N-9 FPGA, custom firmware, and a default RV32I core; they say NextPCB produced the boards and planned to bring 25 to the developer workshop. A logistics update then delayed intended June 8 distribution. The source record supports real physical boards and a 2026 event association, not a final unit count, completed recipient delivery, or the precise current post-event design revision.

Lifecycle

Add-ons & Upgrades

RISC-V Summit Europe 2026 FPGA Badge primary team source detail

documented hardware core

RP2350 and GW1N-9 FPGA core

SemiTO-V identifies an RP2350 microcontroller and GOWIN GW1N-9 FPGA for the badge. The record does not infer unlisted peripherals, power behavior, safety limits, complete bill of materials, or exact population of every physical unit.

Compatibility: SemiTO-V RISC-V FPGA Badge

RISC-V Summit Europe 2026 FPGA Badge README-linked projects; deployed build unrecovered

firmware reference links

Public firmware references

The README points to pico2-editor and riscv-badge-displaylib. This record preserves their public-reference role without asserting version parity, a released binary, a deployed event image, programming steps, support ownership, or a recovery procedure.

Compatibility: riscv-fpga-badge-2026 README

RISC-V Summit Europe 2026 FPGA Badge public native source

hardware source archive

KiCad 10 open-hardware archive

The repository README identifies KiCad 10 and the archive exposes native PCB and schematic files. The open source tree is valuable documentation, but it is not a substitute for a reconciled physical production revision, assembly record, electrical-safety assessment, or delivery ledger.

Compatibility: riscv-fpga-badge-2026 repository

RISC-V Summit Europe 2026 FPGA Badge primary team source detail

high-level firmware capability

RV32I firmware context

The team says the custom firmware includes a default RV32I core. This is recorded as high-level source context only, without operational FPGA configuration, programming, debugging, execution, or security claims.

Compatibility: SemiTO-V RISC-V FPGA Badge

RISC-V Summit Europe 2026 FPGA Badge 25 boards planned; completed recipient handoff unrecovered

limited event initiative

Developer Zone and 25-board source trail

SemiTO-V stated it would bring 25 badges to the Developer Zone workshop and later reported a logistics problem that prevented intended June 8 distribution. The sources establish a limited 25-unit Developer Zone badge run in planning and a real physical-board project, not a completed allocation ledger, attendee-wide issue, or confirmed recipient count.

Compatibility: RISC-V Summit Europe 2026 Developer Zone

RISC-V Summit Europe 2026 FPGA Badge August 3, 2026 source update; event-unit parity unconfirmed

revision boundary

current post-event V1.6 KiCad revision

Version 1.6 fixes listed in the August source commit demonstrate that the public design continued after the June summit. The current post-event V1.6 KiCad revision is therefore not presented as a photograph, render, or authoritative specification of every physical summit badge.

Compatibility: riscv-fpga-badge-2026 Version 1.6

Operational history

Issues & Camp Impact

RISC-V Summit Europe 2026 FPGA Badge note

final hardware, power, and electrical-safety gap · public source archive review · native source visible; production/safety evidence unrecovered

The public KiCad archive and team posts name a controller and FPGA, but reviewed sources do not establish a reconciled manufactured BOM, component substitutions, exact power/battery architecture, charge/protection behavior, electrical limits, thermal result, assembly/test plan, compliance result, enclosure, connector map, or final populated-board condition for physical summit units.

The catalogue preserves the source-backed design trail without calling it a fabrication recipe, tested device specification, safety assessment, or compatibility guarantee.

RISC-V Summit Europe 2026 FPGA Badge note

firmware release and deployed-build gap · README and repository-state review · public references visible; event build unrecovered

The README links firmware-related repositories and team posts name custom firmware plus a default RV32I core, but the project repository has no tag or GitHub release and reviewed sources do not map a versioned build to physical summit boards, provide a final binary, define a support owner, or establish a recovery/update lifecycle.

The record describes public firmware context at a high level without presenting any current source checkout as deployed, supported, verified, or suitable for operation.

RISC-V Summit Europe 2026 FPGA Badge note

individual manufacturing and delivery-role boundary · named design and production-context sources · team/design credits and named production partner recorded; role allocation incomplete

The README names five designers and team sources name SemiTO-V and NextPCB, but reviewed sources do not allocate individual PCB, firmware, FPGA, artwork, review, procurement, assembly, quality-control, logistics, handoff, support, or image-rights roles among the named people or organizations.

The dossier credits named contributors and the stated production partner without inferring sole authorship, manufacture responsibility, fulfilment ownership, product-support duty, or image authority.

RISC-V Summit Europe 2026 FPGA Badge note

license, sponsorship, and event-endorsement boundary · README and team-source statements · hardware-license and named-sponsor claims recorded narrowly

The project README states a CERN-OHL-W hardware license and names RISC-V International, NextPCB, GOWIN Semiconductor, and DeepComputing as sponsors, while team posts associate the badge with the summit. These claims do not by themselves show that event organizers owned the repository, issued the board as a standard credential, endorsed every current revision, or granted image-reuse permission.

The catalogue links the source-license and sponsorship context while keeping organizer ownership, attendee credential status, trademark/endorsement scope, physical-delivery responsibility, and image rights separate.

RISC-V Summit Europe 2026 FPGA Badge note

limited Developer Zone allocation and fulfilment gap · primary team event updates · 25 boards planned; logistics delay published; recipient outcome unrecovered

SemiTO-V said it planned to bring 25 boards to the Developer Zone workshop, then reported that a logistics issue prevented intended June 8 distribution and hoped for June 9 availability. Reviewed sources do not establish a final inventory, distribution date, ticket eligibility, recipient count, pickup process, shipment, replacement, refund, completed handoff, or a universal attendee allocation.

The catalogue does not turn a limited planned workshop allocation into proof that all 25 boards, all workshop participants, or all summit attendees received a badge.

RISC-V Summit Europe 2026 FPGA Badge note

missing rights-cleared image · local project policy and source-revision review · needs a rights-cleared, event-unit-specific original or upstream render

No RISC-V Summit Europe 2026 FPGA Badge image is published because the current repository gallery render is associated with a later revised source tree rather than a confirmed physical summit unit, and the reviewed materials do not provide complete image-specific event-unit status, named attribution, source URL, license or explicit permission basis, and local processing provenance together.

The record remains source-backed and image-free rather than copying repository renders, team social media, event media, screenshots, logos, or approximate/generated imagery.

RISC-V Summit Europe 2026 FPGA Badge note

summit prototype and post-event source-revision boundary · primary team statement and dated repository history · physical initiative established; exact current-source-to-unit mapping unrecovered

The public event-associated material establishes physical boards/prototypes, while a later August Version 1.6 commit fixes design issues and changes silkscreen after the June summit. The reviewed sources do not map the current repository files, gallery render, or all listed fixes to a particular physical summit board.

Current open design sources are linked for research but are not represented as the definitive exact event-unit design, final production revision, or a factual image of every distributed unit.

Resources

SemiTO-V public team profile badge-team profile · Public SemiTO-V profile identifying the Polytechnic of Turin RISC-V student team. It supplies team context rather than an organizer-published distribution record. RISC-V FPGA Badge KiCad PCB native PCB source · Native KiCad PCB source in the public archive. It establishes a real hardware-design trail without proving that every current source change shipped on a 2026 summit unit. RISC-V FPGA Badge KiCad schematic native schematic source · Native top-level KiCad schematic source, retained as a hardware-reference link rather than a fabrication, safety, or production-equivalence assertion. RISC-V Summit Europe 2026 official overview official event site · Official Summit Europe source establishing the June 8-12 Bologna event, its RISC-V technical/developer focus, and the June 8 Developer Workshop context. RISC-V International summit retrospective official post-event context · RISC-V International's public summit page thanks participants for joining RISC-V Summit Europe 2026 in Bologna, confirming that the event occurred. RISC-V Summit Europe 2026 official venue official venue page · Official event source naming Palazzo dei Congressi at Piazza della Costituzione 4/A in Bologna, Italy. OSHWA certification IT000028 open-hardware certification record · Public OSHWA certification record linked by SemiTO-V for the badge project. Certification context does not identify a particular physical summit unit or grant separate provenance for a selected image. SemiTO-V RISC-V FPGA Badge repository open-hardware source archive · Public project repository described as an electronic badge PCB for RISC-V Summit Europe 2026 in Bologna. It provides source-tree, license, and current-revision context but has no GitHub tag or release. Version 1.6 KiCad source revision post-event source revision · Dated August 3, 2026 project commit whose message identifies Version 1.6 fixes to FB3, a secondary-flash pull-up, a battery diode, alignment, and silkscreen. It is later than the June summit and is not treated as proof of the exact event-unit revision. SemiTO-V Developer Zone badge post primary badge-team event update · Primary team statement that it volunteered in the Developer Zone with a custom electronic PCB badge for the summit, naming RP2350, GW1N-9, custom firmware, default RV32I core, NextPCB production, and a planned 25-board workshop allocation. SemiTO-V OSHWA and production post primary badge-team provenance update · Primary team post calling the board an electronic badge designed for the summit, noting OSHWA certification and that production files were sent to NextPCB. It is team-published evidence, not a general-attendee issuance announcement. RISC-V FPGA Badge README project overview and credit record · Project README naming the badge, KiCad 10, firmware references, named designers, named sponsors, and CERN-OHL-W hardware-license claim. Its current gallery rasters are not selected as local images because their exact summit-unit revision and image-specific processing provenance are unresolved.

Sources

Open Source Hardware Association: OSHWA IT000028 Retrieved 2026-05-15 · Public certification record cited by SemiTO-V for this project. It corroborates the open-hardware trail without resolving event allocation or image provenance. RISC-V International: RISC-V International summit page Retrieved 2026-05-15 · Primary official post-event source thanking participants for joining the 2026 Bologna summit. RISC-V Summit Europe: RISC-V Summit Europe 2026 Retrieved 2026-05-15 · Primary official event source for the June 8-12 Bologna summit and Developer Workshop context. RISC-V Summit Europe: RISC-V Summit Europe 2026 venue Retrieved 2026-05-15 · Primary official venue source for Palazzo dei Congressi, Piazza della Costituzione 4/A, Bologna. SemiTO-V: SemiTO-V Developer Zone RISC-V FPGA Badge update Retrieved 2026-05-15 · Primary badge-team event update naming the RP2350, GW1N-9 FPGA, custom firmware, default RV32I core, NextPCB production, volunteer Developer Zone role, and planned 25-board workshop allocation. SemiTO-V: SemiTO-V OSHWA certification and production update Retrieved 2026-05-15 · Primary badge-team post that calls the board an electronic badge designed for the summit, records OSHWA certification, and says production files went to NextPCB. SemiTO-V: SemiTO-V RISC-V student team profile Retrieved 2026-05-15 · Primary team profile establishing SemiTO-V as a Polytechnic of Turin RISC-V student team and project publisher. SemiTO-V / GitHub: RISC-V FPGA Badge KiCad PCB source Retrieved 2026-05-15 · Primary native PCB source for the public hardware design trail; not a claim that its present branch exactly matches all physical summit boards. SemiTO-V / GitHub: RISC-V FPGA Badge KiCad schematic source Retrieved 2026-05-15 · Primary native schematic source for the public hardware design trail; not a production BOM, electrical-safety result, or final-unit equivalence record. SemiTO-V / GitHub: RISC-V FPGA Badge Version 1.6 Retrieved 2026-05-15 · Primary dated August 3, 2026 source revision. Its post-summit fixes establish a revision boundary between current design files and a confirmed physical summit-unit configuration. SemiTO-V / GitHub: RISC-V Summit Europe 2026 Badge README Retrieved 2026-05-15 · Primary project README for KiCad 10, firmware-reference links, named designers, named sponsors, CERN-OHL-W source-license statement, and current gallery asset context. SemiTO-V / GitHub: semitov/riscv-fpga-badge-2026 Retrieved 2026-05-15 · Primary open-hardware repository whose description identifies an electronic badge PCB for the 2026 Bologna RISC-V Summit Europe.