Issue dossier
The public KiCad archive and team posts name a controller and FPGA, but reviewed sources do not establish a reconciled manufactured BOM, component substitutions, exact power/battery architecture, charge/protection behavior, electrical limits, thermal result, assembly/test plan, compliance result, enclosure, connector map, or final populated-board condition for physical summit units.
A linkable camp-impact record with badge context, severity, evidence confidence, and source notes.
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final hardware, power, and electrical-safety gap · public source archive review · native source visible; production/safety evidence unrecovered
The catalogue preserves the source-backed design trail without calling it a fabrication recipe, tested device specification, safety assessment, or compatibility guarantee.
- Badge
- RISC-V Summit Europe 2026 FPGA Badge
- Category
- final hardware, power, and electrical-safety gap
- Severity
- note
- Confidence
- public source archive review
- Status
- native source visible; production/safety evidence unrecovered
- Timeframe
- current catalogue build
- Source note
- SemiTO-V repository tree, KiCad sources, README, and primary team posts.
badge-team profile
Public SemiTO-V profile identifying the Polytechnic of Turin RISC-V student team. It supplies team context rather than an organizer-published distribution record.
Badge: RISC-V Summit Europe 2026 FPGA Badge
native PCB source
Native KiCad PCB source in the public archive. It establishes a real hardware-design trail without proving that every current source change shipped on a 2026 summit unit.
Badge: RISC-V Summit Europe 2026 FPGA Badge
native schematic source
Native top-level KiCad schematic source, retained as a hardware-reference link rather than a fabrication, safety, or production-equivalence assertion.
Badge: RISC-V Summit Europe 2026 FPGA Badge
official event site
Official Summit Europe source establishing the June 8-12 Bologna event, its RISC-V technical/developer focus, and the June 8 Developer Workshop context.
Badge: RISC-V Summit Europe 2026 FPGA Badge
official post-event context
RISC-V International's public summit page thanks participants for joining RISC-V Summit Europe 2026 in Bologna, confirming that the event occurred.
Badge: RISC-V Summit Europe 2026 FPGA Badge
official venue page
Official event source naming Palazzo dei Congressi at Piazza della Costituzione 4/A in Bologna, Italy.
Badge: RISC-V Summit Europe 2026 FPGA Badge
open-hardware certification record
Public OSHWA certification record linked by SemiTO-V for the badge project. Certification context does not identify a particular physical summit unit or grant separate provenance for a selected image.
Badge: RISC-V Summit Europe 2026 FPGA Badge
open-hardware source archive
Public project repository described as an electronic badge PCB for RISC-V Summit Europe 2026 in Bologna. It provides source-tree, license, and current-revision context but has no GitHub tag or release.
Badge: RISC-V Summit Europe 2026 FPGA Badge
post-event source revision
Dated August 3, 2026 project commit whose message identifies Version 1.6 fixes to FB3, a secondary-flash pull-up, a battery diode, alignment, and silkscreen. It is later than the June summit and is not treated as proof of the exact event-unit revision.
Badge: RISC-V Summit Europe 2026 FPGA Badge
primary badge-team event update
Primary team statement that it volunteered in the Developer Zone with a custom electronic PCB badge for the summit, naming RP2350, GW1N-9, custom firmware, default RV32I core, NextPCB production, and a planned 25-board workshop allocation.
Badge: RISC-V Summit Europe 2026 FPGA Badge
primary badge-team provenance update
Primary team post calling the board an electronic badge designed for the summit, noting OSHWA certification and that production files were sent to NextPCB. It is team-published evidence, not a general-attendee issuance announcement.
Badge: RISC-V Summit Europe 2026 FPGA Badge
project overview and credit record
Project README naming the badge, KiCad 10, firmware references, named designers, named sponsors, and CERN-OHL-W hardware-license claim. Its current gallery rasters are not selected as local images because their exact summit-unit revision and image-specific processing provenance are unresolved.
Badge: RISC-V Summit Europe 2026 FPGA Badge
Open Source Hardware Association · retrieved 2026-05-15
Public certification record cited by SemiTO-V for this project. It corroborates the open-hardware trail without resolving event allocation or image provenance.
Badge: RISC-V Summit Europe 2026 FPGA Badge
RISC-V International · retrieved 2026-05-15
Primary official post-event source thanking participants for joining the 2026 Bologna summit.
Badge: RISC-V Summit Europe 2026 FPGA Badge
RISC-V Summit Europe · retrieved 2026-05-15
Primary official event source for the June 8-12 Bologna summit and Developer Workshop context.
Badge: RISC-V Summit Europe 2026 FPGA Badge
RISC-V Summit Europe · retrieved 2026-05-15
Primary official venue source for Palazzo dei Congressi, Piazza della Costituzione 4/A, Bologna.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V · retrieved 2026-05-15
Primary badge-team event update naming the RP2350, GW1N-9 FPGA, custom firmware, default RV32I core, NextPCB production, volunteer Developer Zone role, and planned 25-board workshop allocation.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V · retrieved 2026-05-15
Primary badge-team post that calls the board an electronic badge designed for the summit, records OSHWA certification, and says production files went to NextPCB.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V · retrieved 2026-05-15
Primary team profile establishing SemiTO-V as a Polytechnic of Turin RISC-V student team and project publisher.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V / GitHub · retrieved 2026-05-15
Primary native PCB source for the public hardware design trail; not a claim that its present branch exactly matches all physical summit boards.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V / GitHub · retrieved 2026-05-15
Primary native schematic source for the public hardware design trail; not a production BOM, electrical-safety result, or final-unit equivalence record.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V / GitHub · retrieved 2026-05-15
Primary dated August 3, 2026 source revision. Its post-summit fixes establish a revision boundary between current design files and a confirmed physical summit-unit configuration.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V / GitHub · retrieved 2026-05-15
Primary project README for KiCad 10, firmware-reference links, named designers, named sponsors, CERN-OHL-W source-license statement, and current gallery asset context.
Badge: RISC-V Summit Europe 2026 FPGA Badge
SemiTO-V / GitHub · retrieved 2026-05-15
Primary open-hardware repository whose description identifies an electronic badge PCB for the 2026 Bologna RISC-V Summit Europe.
Badge: RISC-V Summit Europe 2026 FPGA Badge