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Buffered CLK and inverted nCLK outputs

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BSides Brisbane 2026 Clock Module Badge official README documented

hardware interface

The documented discrete 2N7000 output stage provides normal CLK and inverted nCLK outputs for slow digital-logic or teaching experiments, with an LED pulse indication.

Badge
BSides Brisbane 2026 Clock Module Badge
Type
hardware interface
Status
official README documented
Compatibility
BSides Brisbane 2026 Clock Module; regulated +5 V input
Source
https://github.com/bsidesbrisbane/badge-2026/blob/58a7d9b2e9502cb689f52f1f6826bfcaa90e214c/README.md

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Source trail

Evidence Sources

BSides Brisbane / GitHub · retrieved 2026-05-15

bsidesbrisbane/badge-2026

Public source archive named `Repo for the BSides Brisbane 2026 Badge`, created on 2026-07-10 after the July 4 event. The pinned snapshot carries no tag or GitHub release, so it documents the project source rather than a release-bound deployed build.

Badge: BSides Brisbane 2026 Clock Module Badge